Methods and apparatus to autonomously detect thermal anomalies

ABSTRACT

Methods, apparatus, systems, and articles of manufacture are disclosed to autonomously detect thermal anomalies. Disclosed examples include an example apparatus to detect engine anomalies comprising: at least one memory; instructions in the apparatus; and processor circuitry to execute the instructions to: control a plurality of infrared cameras to capture a baseline image set, the baseline image set including at least two thermal images; generate emissivity data based on the baseline image set; provide the baseline image set and the emissivity data to an artificial intelligence model, the artificial intelligence model to generate a reconstructed image set; determine a difference between the baseline image set and the reconstructed image set; and in response to the difference exceeding a threshold, generate an alert indicating detection of an engine anomaly.

FIELD OF THE DISCLOSURE

This disclosure relates generally to anomaly detection and, moreparticularly, to methods and apparatus to autonomously detect thermalanomalies.

BACKGROUND

In recent years, miniaturization of sensors has made a wider set oflocations available for placement of these sensors. However, somelocations include high temperatures and/or other harsh conditions thatcan damage the sensors.

One environment that benefits from sensors to monitor the environment isa gas turbine. Gas turbines typically include a turbine casing disposedabout hot gas components, with a cowl disposed about the casing. Manyturbines include an annular cavity between the casing and the cowl, withturbine components disposed within the annular cavity. Hot fluidsflowing within the turbine may radiate heat to the annular cavity andcause turbine components to reach undesirable temperatures. Areas ofabnormally high temperature near turbine components can degrade thecomponents more quickly and reduce the operating lifetime of thecomponents.

As such, there is a need for sensors able to withstand highertemperatures across the aerospace, power, transportation, and medicalindustries. Additionally, there is a need for methods to manage suchsensors in high temperature environments.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of an example turbofan gas turbineengine in which examples disclosed herein may be implemented.

FIG. 2 is an illustration of an example autonomous sensor array that maybe part of an example system to detect thermal anomalies.

FIG. 3 is an illustration of the example system to detect thermalanomalies.

FIG. 4 is another illustration of the example system to detect thermalanomalies.

FIG. 5A illustrates an example operating environment without a thermalanomaly.

FIG. 5B illustrates an example operating environment with a thermalanomaly.

FIG. 6 illustrates example infrared images being operated on andtransmitted as input to a trained vector quantized variationalautoencoder.

FIG. 7 illustrates example images from the example system to detectthermal anomalies.

FIG. 8 is an illustration of representative of example machine readableinstructions that may be executed by example processor circuitry totrain the vector quantized variational autoencoder.

FIG. 9 is an illustration of representative of example machine readableinstructions that may be executed by example processor circuitry tooperate the vector quantized variational autoencoder.

FIG. 10 is a block diagram of an example processing platform includingprocessor circuitry structured to execute the example machine readableinstructions of FIGS. 8-9 to implement the anomaly detecting system ofFIG. 3 .

FIG. 11 is a block diagram of an example implementation of the processorcircuitry of FIG. 10 .

FIG. 12 is a block diagram of another example implementation of theprocessor circuitry of FIG. 10 .

The figures are not to scale. Instead, the thickness of the layers orregions may be enlarged in the drawings. Although the figures showlayers and regions with clean lines and boundaries, some or all of theselines and/or boundaries may be idealized. In reality, the boundariesand/or lines may be unobservable, blended, and/or irregular. In general,the same reference numbers will be used throughout the drawing(s) andaccompanying written description to refer to the same or like parts. Asused herein, unless otherwise stated, the term “above” describes therelationship of two parts relative to Earth. A first part is above asecond part, if the second part has at least one part between Earth andthe first part. Likewise, as used herein, a first part is “below” asecond part when the first part is closer to Earth than the second part.As noted above, a first part can be above or below a second part withone or more of: other parts therebetween, without other partstherebetween, with the first and second parts touching, or without thefirst and second parts being in direct contact with one another. As usedin this patent, stating that any part (e.g., a layer, film, area,region, or plate) is in any way on (e.g., positioned on, located on,disposed on, or formed on, etc.) another part, indicates that thereferenced part is either in contact with the other part, or that thereferenced part is above the other part with one or more intermediatepart(s) located therebetween. As used herein, connection references(e.g., attached, coupled, connected, and joined) may includeintermediate members between the elements referenced by the connectionreference and/or relative movement between those elements unlessotherwise indicated. As such, connection references do not necessarilyinfer that two elements are directly connected and/or in fixed relationto each other. As used herein, stating that any part is in “contact”with another part is defined to mean that there is no intermediate partbetween the two parts.

Unless specifically stated otherwise, descriptors such as “first,”“second,” “third,” etc., are used herein without imputing or otherwiseindicating any meaning of priority, physical order, arrangement in alist, and/or ordering in any way, but are merely used as labels and/orarbitrary names to distinguish elements for ease of understanding thedisclosed examples. In some examples, the descriptor “first” may be usedto refer to an element in the detailed description, while the sameelement may be referred to in a claim with a different descriptor suchas “second” or “third.” In such instances, it should be understood thatsuch descriptors are used merely for identifying those elementsdistinctly that might, for example, otherwise share a same name. In someexamples used herein, the term “substantially” is used to describe arelationship between two parts that is within three degrees of thestated relationship (e.g., a substantially colinear relationship iswithin three degrees of being linear, a substantially perpendicularrelationship is within three degrees of being perpendicular, asubstantially parallel relationship is within three degrees of beingparallel, etc.).

As used herein, “approximately” and “about” refer to dimensions that maynot be exact due to manufacturing tolerances and/or other real worldimperfections. As used herein “substantially real time” refers tooccurrence in a near instantaneous manner recognizing there may be realworld delays for computing time, transmission, etc. Thus, unlessotherwise specified, “substantially real time” refers to real time +/- 1second. As used herein, the phrase “in communication,” includingvariations thereof, encompasses direct communication and/or indirectcommunication through one or more intermediary components, and does notrequire direct physical (e.g., wired) communication and/or constantcommunication, but rather additionally includes selective communicationat periodic intervals, scheduled intervals, aperiodic intervals, and/orone-time events. As used herein, “processor circuitry” is defined toinclude (i) one or more special purpose electrical circuits structuredto perform specific operation(s) and including one or moresemiconductor-based logic devices (e.g., electrical hardware implementedby one or more transistors), and/or (ii) one or more general purposesemiconductor-based electrical circuits programmed with instructions toperform specific operations and including one or moresemiconductor-based logic devices (e.g., electrical hardware implementedby one or more transistors). Examples of processor circuitry includeprogrammed microprocessors, Field Programmable Gate Arrays (FPGAs) thatmay instantiate instructions, Central Processor Units (CPUs), GraphicsProcessor Units (GPUs), Digital Signal Processors (DSPs), XPUs, ormicrocontrollers and integrated circuits such as Application SpecificIntegrated Circuits (ASICs). For example, an XPU may be implemented by aheterogeneous computing system including multiple types of processorcircuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs,one or more DSPs, etc., and/or a combination thereof) and applicationprogramming interface(s) (API(s)) that may assign computing task(s) towhichever one(s) of the multiple types of the processing circuitryis/are best suited to execute the computing task(s).

DETAILED DESCRIPTION

Aircrafts include engines, which act as a propulsion system to generatemechanical power and forces such as thrust. A gas turbine, also called acombustion turbine or a turbine engine, is a type of internal combustionengine that can be implemented in the propulsion system of an aircraft.For example, a gas turbine can be implemented in connection with aturbofan or a turbojet aircraft engine. Gas turbines also havesignificant applications in areas such as industrial power generation.

The area under a cowling in a gas turbine engine is normally exposed tosignificant heat. Accordingly, the components of gas turbine engines aredesigned to withstand such normal operating temperatures. However,certain anomalies (e.g., an engine leak) can cause engine components toexceed normal operating temperatures. Abnormal engine temperatures candamage under-cowl components. Thus, discovering and addressing suchanomalies is an important part of operating a gas turbine engine.

The traditional method of discovering anomalies in the under-cowlenvironment is a lengthy, inefficient, and often insufficient process.First, in response to a thermocouple detecting excessive temperature inan engine, the engine is shut down. Next, any casing covering anunder-cowl area is removed to expose the under-cowl area. A safetyoperator then sprays heat sensitive materials on areas of suspectedleakage. The engine is next re-started and taken to normal operationaltemperatures. After shutting down the engine and allowing the engine tocool, the under-cowl area is opened again. The safety operator thenre-inspects the heat sensitive materials. By analyzing these materials,the safety operator can determine if they have found the leak. If theydid not find the leak, the process repeats. This trial-and-errorapproach is time consuming and costly, often resulting in missed leaksor significant downtime while a leak is located.

An alternative approach uses multiple fixed infrared (IR) cameras tomonitor the under-cowl area. Fixed IR cameras can generate a first imageset by capturing images of an engine operating under normal conditions.The first image set can be compared to images of the same engine underdifferent operating conditions. For example, the fixed IR cameras cancapture additional images, generating a second image set. Then, thesecond image set can be directly compared to the first image set toidentify anomalies. An image comparison may be carried out by safetypersonnel. Alternatively, various computer-based comparison methods canbe used to compare image sets. By identifying differences between theimage sets, anomalies can be detected and corrective measures can betaken.

Methods including fixed IR cameras and direct image comparison improveupon traditional anomaly detection methods, but still have significantshortcomings. Direct programmatic comparison (e.g., a pixel by pixelcomparison) can generally only be effectively carried out when the firstand second image sets overlap. As the area of coverage increases,storing enough images of normal operation becomes infeasible.Additionally, any slight change in the environment (even one unrelatedto a thermal anomaly) can cause a false positive result.

This inflexibility reduces the effectiveness of IR camera arrays in theunder-cowl environment. Furthermore, massive datasets andcomputationally complex comparison algorithms may involve significantcomputing power and time to execute. Various methods have been proposedto overcome these shortcomings. However, there has not yet been a systemto efficiently facilitate autonomous detection of leaks acrossdistributed infrared camera sources. Examples described herein useartificial intelligence (AI) camera control systems to generatesubstantially real-time engine surface temperature maps andautomatically identify anomalies.

In some examples, this is achieved by first training a vector quantizedvariational autoencoder on a baseline infrared image set includingmultiple color channels supplemented with emissivity data generated fromthe baseline image set. The trained vector quantized variational encodercan be used to create a reconstructed image set from any image set(e.g., a baseline image set). A thermal anomaly may be detected if aratio of the baseline image set to the reconstructed image set is abovea threshold. In response, a communication can be transmitted to a safetysystem. In some examples, the safety system can initiate a notificationand/or initiate corrective action.

Furthermore, such thermal anomaly detection could benefit any systemseeking to monitor and/or prevent excessive temperatures. Example usecases can be found across the aerospace, power, transportation, andmedical industries.

In the following detailed description, reference is made to theaccompanying drawings that form a part hereof, and in which is shown byway of illustration specific examples that may be practiced. Theseexamples are described in sufficient detail to enable one skilled in theart to practice the subject matter, and it is to be understood thatother examples may be utilized. The following detailed description istherefore, provided to describe example implementations and not to betaken limiting on the scope of the subject matter described in thisdisclosure. Certain features from different aspects of the followingdescription may be combined to form yet new aspects of the subjectmatter discussed below.

When introducing elements of various embodiments of the presentdisclosure, the articles “a,” “an,” “the,” and “said” are intended tomean that there are one or more of the elements.

The terms “upstream” and “downstream” refer to the relative directionwith respect to fluid flow in a fluid pathway. For example, “upstream”refers to the direction from which the fluid flows, and “downstream”refers to the direction to which the fluid flows.

As used herein, the terms “axial” and “longitudinal” both refer to adirection parallel to the centerline axis of a gas turbine (e.g., aturbofan, a core gas turbine engine, etc.), while “radial” refers to adirection perpendicular to the axial direction, and “tangential” or“circumferential” refers to a direction mutually perpendicular to theaxial and radial directions. Accordingly, as used herein, “radiallyinward” refers to the radial direction from the outer circumference ofthe gas turbine towards the centerline axis of the gas turbine, and“radially outward” refers to the radial direction from the centerlineaxis of the gas turbine towards the outer circumference of gas turbine.As used herein, the terms “forward”, “fore”, and “front” refer to alocation relatively upstream in an air flow passing through or around acomponent, and the terms “aft” and “rear” refer to a location relativelydownstream in an air flow passing through or around a component.

FIG. 1 is a schematic cross-sectional view of a prior art turbofan-typegas turbine engine 100 (“turbofan 100”). As shown in FIG. 1 , theturbofan 100 defines a longitudinal or axial centerline axis 102extending therethrough for reference. In general, the turbofan 100 mayinclude a core turbine 104 or gas turbine engine disposed downstreamfrom a fan section 106.

The core turbine 104 generally includes a substantially tubular outercasing 108 (“turbine casing 108”) that defines an annular inlet 110. Theouter casing 108 can be formed from a single casing or multiple casings.The outer casing 108 encloses, in serial flow relationship, a compressorsection having a booster or low pressure compressor 112 (“LP compressor112”) and a high pressure compressor 114 (“HP compressor 114”), acombustion section 116, a turbine section having a high pressure turbine118 (“HP turbine 118”) and a low pressure turbine 120 (“LP turbine120”), and an exhaust section 122. A high pressure shaft or spool 124(“HP shaft 124”) drivingly couples the HP turbine 118 and the HPcompressor 114. A low pressure shaft or spool 126 (“LP shaft 126”)drivingly couples the LP turbine 120 and the LP compressor 112. The LPshaft 126 may also couple to a fan spool or shaft 128 of the fan section106 (“fan shaft 128”). In some examples, the LP shaft 126 may coupledirectly to the fan shaft 128 (e.g., a direct-drive configuration). Inalternative configurations, the LP shaft 126 may couple to the fan shaft128 via a reduction gearbox 130 (e.g., an indirect-drive or geared-driveconfiguration).

As shown in FIG. 1 , the fan section 106 includes a plurality of fanblades 132 coupled to and extending radially outwardly from the fanshaft 128. An annular fan casing or nacelle 134 circumferentiallyencloses the fan section 106 and/or at least a portion of the coreturbine 104. The nacelle 134 is supported relative to the core turbine104 by a plurality of circumferentially-spaced apart outlet guide vanes136. Furthermore, a downstream section 138 of the nacelle 134 canenclose an outer portion of the core turbine 104 to define a bypassairflow passage 140 therebetween.

As illustrated in FIG. 1 , air 142 enters an inlet portion 144 of theturbofan 100 during operation thereof. A first portion 146 of the air142 flows into the bypass airflow passage 140, while a second portion148 of the air 142 flows into the annular inlet 110 of the LP compressor112. One or more sequential stages of LP compressor stator vanes 150 andLP compressor rotor blades 152 coupled to the LP shaft 126 progressivelycompress the second portion 148 of the air 142 flowing through the LPcompressor 112 en route to the HP compressor 114. Next, one or moresequential stages of HP compressor stator vanes 154 and HP compressorrotor blades 156 coupled to the HP shaft 124 further compress the secondportion 148 of the air 142 flowing through the HP compressor 114. Thisprovides compressed air 158 to the combustion section 116 where it mixeswith fuel and burns to provide combustion gases 160.

The combustion gases 160 flow through the HP turbine 118 in which one ormore sequential stages of HP turbine stator vanes 162 and HP turbinerotor blades 164 coupled to the HP shaft 124 extract a first portion ofkinetic and/or thermal energy from the combustion gases 160. This energyextraction supports operation of the HP compressor 114. The combustiongases 160 then flow through the LP turbine 120 where one or moresequential stages of LP turbine stator vanes 166 and LP turbine rotorblades 168 coupled to the LP shaft 126 extract a second portion ofthermal and/or kinetic energy therefrom. This energy extraction causesthe LP shaft 126 to rotate, thereby supporting operation of the LPcompressor 112 and/or rotation of the fan shaft 128. The combustiongases 160 then exit the core turbine 104 through the exhaust section 122thereof.

Along with the turbofan 100, the core turbine 104 serves a similarpurpose and sees a similar environment in land-based gas turbines,turbojet engines in which the ratio of the first portion 146 of the air142 to the second portion 148 of the air 142 is less than that of aturbofan, and unducted fan engines in which the fan section 106 isdevoid of the nacelle 134. In each of the turbofan, turbojet, andunducted engines, a speed reduction device (e.g., the reduction gearbox130) may be included between any shafts and spools. For example, thereduction gearbox 130 may be disposed between the LP shaft 126 and thefan shaft 128 of the fan section 106. FIG. 1 further includes a cowling170 and IR cameras 172-176. The operation of the IR cameras 172-176 todetect thermal anomalies will be described in detail in association withFIGS. 2-13 .

FIG. 2 is an illustration of an example system to detect thermalanomalies. FIG. 2 includes an operating environment 200 and under-cowlcomponents 202. FIG. 2 also shows the IR cameras 172-176, which in someexamples coordinate to detect thermal anomalies. FIG. 2 also includes anexample offset-arch gimbal 178.

The IR cameras 172-176 detect thermal energy emitted from theenvironment and convert the thermal energy into an electronic signal.The electronic signal can be monitored and analyzed with processorcircuitry. Additionally, the IR cameras 172-176 are disposed withinoffset-arch gimbals (e.g., the example offset-arch gimbal 178.)Offset-arch gimbals provide pan/tilt capabilities, increasing the areaof coverage of the IR cameras 172-176.

To facilitate pan/tilt capabilities, the example offset-arch gimbal 178includes two arched rack and pinions disposed orthogonally to eachother. In operation, a gimbal body, a sensor platform, a sensor (e.g.,IR camera 174), and any other coupled components are simultaneouslytilted as a first pinion moves about a first arched rack. As the firstarched rack follows a generally curved shape, movement about the racksimultaneously translates and rotates these elements. A second archedrack placed orthogonally to the first arched rack functions similarly.Translation of the IR camera 174 causes a focal point of the IR camerato move. By moving the focal point of the IR camera 174, an area ofcoverage can be increased while decreasing a window size associated witha sensor within an enclosure. In the example of FIG. 2 , IR cameras 172and 176 are also disposed in offset-arch gimbals.

The IR cameras 172-176 also include specialized circuitry and/orinstructions to coordinate with other offset-arch gimbal systems tocover a larger area. In the operating environment 200, the IR camera172, the IR camera 174, and the IR camera 176 can coordinate together tocover an under-cowl area and detect thermal anomalies and/or otheranomalies. Thermal anomalies may be associated with any of theunder-cowl components 202. In some examples, the IR cameras may bemovable (e.g., coupled to an autonomous drone) to facilitate a greaterarea of coverage.

FIG. 3 is an illustration of an example system 300 to detect thermalanomalies. The system 300 includes an example analysis server 304 andthe operating environment 200 of FIG. 2 . The system 300 is additionallyconnected to a safety system 302 via a network 312.

The example analysis server 304 further includes example anomalydetecting circuitry 306, example database managing circuitry 308, and anexample database 310. Although the analysis server 304 is illustratedseparately from the operating environment 200, the analysis server 304may instead be part of the operating environment 200. For example, theanalysis server 304 may be included in a small computing device withinthe operating environment 200 (e.g., a microcontroller) or may bedirectly integrated into the circuitry of the example IR cameras172-176.

To store images from the IR cameras 172-176 and/or other data fordetecting thermal anomalies, the analysis server 304 further includesthe database managing circuitry 308 and the database 310. The databasemanaging circuitry 308 accesses the database 310 to store and/orretrieve information. The example database 310 stores thermal images,emissivity data, weights for artificial intelligence circuitry 406discussed below in connection with FIG. 4 , camera operation statistics,etc.

In some examples, when the system 300 detects a thermal anomaly, thesystem 300 sends a communication to the safety system 302. In someexamples, the communication may cause the safety system 302 to generatea visual, audio, and/or electronic alert (e.g., alert an aircraftoperator). In some examples, the analysis server 304 may insteadcommunicate with an outside server, a cloud server, a third partyentity, etc. In some examples, the safety system 302 may store imagesand/or a recording of the anomaly for later analysis. Stored imagesand/or recordings of anomalies may additionally or alternatively be sentto a safety operator.

FIG. 4 is another illustration of the example system 300 to detectthermal anomalies. FIG. 4 illustrates the analysis server 304 of FIG. 3in greater detail. Specifically, the anomaly detecting circuitry 306includes example camera controller circuitry 402, example infrared imageprocessing circuitry 404, example artificial intelligence circuitry 406,example network interface circuitry 408, example image comparatorcircuitry 410 and example alerting circuitry 412.

FIG. 4 provides an alternate illustration of the operating environment200. The operating environment 200 includes normal thermal areas 418A-Cas well as a thermal anomaly 420. In this illustration, the IR cameras172-176 can be seen coordinating to detect the thermal anomaly 420.

The example infrared cameras 172-176 are controlled by the examplecamera controller circuitry 402. The camera controller circuitry 402 candetect leaks and track them across distributed IR-camera sources. Thecamera controller circuitry 402 may use AI camera control techniques tocapture images for use in generation of a substantially real-time enginesurface temperature tracking map. By using a two dimensional temperaturemap created by the artificial intelligence circuitry 406, the cameracontroller circuitry 402 can coordinate the IR cameras 172-176 to focuson areas with potential thermal anomalies. In the example of FIG. 4 , IRcamera 176 has detected the thermal anomaly 420. In some examples, inresponse to detecting the thermal anomaly 420, the camera controllercircuitry 402 can direct a second IR camera (e.g., IR camera 174) toconfirm the thermal anomaly 420. In some examples, in response to the IRcamera 176 detecting the thermal anomaly 420, the camera controllercircuitry 402 may direct at least one of the IR cameras 172-176 to scanthe thermal anomaly 420 to determine a boundary (e.g., a border) of thethermal anomaly 420.

IR cameras 172-176 take in infrared rays irradiated from the area ofcoverage and convert the infrared rays into images for use by theinfrared image processing circuitry 404. The example infrared imageprocessing circuitry may perform a preprocessing on an infrared image todenoise the infrared image. The infrared image processing circuitry 404can additionally split an image into multiple color channels for use bythe artificial intelligence circuitry 406.

In some examples, the IR cameras 172-176 are supplemented by additionalRGB (e.g., visible imaging) cameras. The infrared image processingcircuitry 404 can then generate emissivity data from captured images ifthere are more than two wavelengths detected. For example, a visibleimage and an infrared camera image can be used to determine emissivitybased on multi-color pyrometry.

Infrared images and emissivity data can be provided to the exampleartificial intelligence circuitry 406. The example artificialintelligence circuitry 406 includes a vector quantized variationalautoencoder (VQVAE). The VQVAE is a deep learning based generative AImethod that finds an underlying (e.g., latent) representation for agiven set of raw data.

For example, the artificial intelligence circuitry 406 can find anunderlying representation for a normal thermal image set. Identificationof the underlying representation is done with a neural network of twoparts, an encoder network and a decoder network. The encoder and decoderare connected through a lower dimensional space that serves as abottleneck. The bottleneck prompts the VQVAE to find a reduced set offeatures (e.g., underlying representation) of the normal thermal images.By training the neural network on a set of images at normal operatingtemperatures, the neural network can find an underlying datadistribution within the normal images. After training, if an image witha thermal anomaly is provided to the VQVAE as input, the VQVAE outputimage will be significantly different from the input. The difference canbe used to determine a presence of a thermal anomaly. Additionally, theneural network training may include data and/or captured images frommore than one engine (e.g., a fleet of engines), which may furtherimprove accuracy.

In some examples, the artificial intelligence circuitry 406 includessupervised and/or unsupervised machine learning models. For example, theartificial intelligence circuitry 406 may be based on a logisticregression model, which classifies an input as either a thermal anomalyor a normal image. In some examples, the artificial intelligencecircuitry 406 includes a generative adversarial network. The artificialintelligence circuitry 406 may also include more than one artificialintelligence model (e.g., a vector quantized variational autoencoder anda generative adversarial network).

The example network interface circuitry 408 connects the analysis server304 to the database managing circuitry 308 and the operating environment200, and provides connectivity to other networked system(s) (e.g., thesafety system 302). The image comparator circuitry 410 determines adifference between two images. In some examples, the image comparatorcircuitry 410 determines a ratio between an input to the AI circuitry406 and an output of the AI circuitry 406.

In some examples, the difference may be based on an absolute value of adifference between corresponding pixel values. In some examples, thedifference is determined based on a ratio of a first image to a secondimage. For example, a ratio value greater than one and less than 2 mayindicate an anomaly. In any of the preceding examples, a neighboringarea estimation can be used to reduce the effect of noise on an outputand reduce false positives. The neighboring area estimation determines asecond difference between an area including a potential anomaly and anarea surrounding the potential anomaly, generating an alert when thesecond difference is larger than a threshold value.

If a difference is greater than a predefined threshold, the examplealerting circuitry 412 can send a communication through the networkinterface circuitry 408 to the safety system 302 of FIG. 3 .Alternatively, the database managing circuitry 308 may store a result.The database managing circuitry 308 may additionally store thermalimages, emissivity data, weights for the AI circuitry 406, and/or cameraoperation statistics.

FIG. 5A illustrates the example operating environment 200 without athermal anomaly. In this example, the IR cameras 172-176 are operatingaccording to a routine defined by the camera controller circuitry 402 ofFIG. 4 . In this example, IR cameras 172, 174, and 176 each image aseparate area. In some examples, an imaging routine may be based on aheat map, areas of prior anomalies, and/or an area of high importance.

FIG. 5B illustrates an example operating environment 200 with thethermal anomaly 420. In this illustration, the IR camera 176 hasdetected the thermal anomaly 420. In response, the IR cameras 172 and174 have deviated from their normal imaging routine in order to analyzethe thermal anomaly 420. In the example illustration of FIG. 5B, the IRcameras 172 and 174 confirm the presence of the thermal anomaly 420. Insome examples, one of the plurality of IR cameras 172-176 may detect theexample thermal anomaly 420 based on a first captured image, and asecond one of the plurality of IR cameras may receive instructions tocapture a second image of the thermal anomaly 420. In such an example,if the second IR camera does not detect an anomaly, the result may beclassified as a false positive.

If no thermal anomaly is detected, IR cameras 172-176 may operate in anormal imaging mode. In the normal imaging mode, the IR cameras 172-176may follow a predefined routine based on a specific area of coverage.

For example, in the normal imaging mode, the camera controller circuitry402 may operate the IR cameras 172-176 to generally image an area ofcoverage in a left-to-right, top-to-bottom manner. In some examples, thecamera controller circuitry 402 can follow a pre-defined pattern/imagingroutine which is stored in the database 310 and retrieved by thedatabase managing circuitry 308.

In response to detection of an anomaly, the camera controller circuitry402 may enter an anomaly analysis mode. In the anomaly analysis mode,the IR cameras 172-176 can deviate from the normal imaging routine toanalyze the anomaly (e.g., the thermal anomaly 420.) In the anomalyanalysis mode, the camera controller circuitry 402 may receive alocation of the thermal anomaly 420, for example. In response, thecamera controller circuitry 402 can direct the IR cameras 172-176 to thelocation of the thermal anomaly 420.

FIG. 6 illustrates example infrared images being operated on andtransmitted as input to a trained VQVAE. FIG. 6 includes an exampleinfrared image set 600, an example first color 602, an example secondcolor 604, an example third color 606, an example emissivity 608, anexample first temperature 610, an example second temperature 612, anexample third temperature 616, and an example variational autoencoderinput 620.

The example infrared image set 600 goes through a series of operationsby the infrared image processing circuitry 404 before being provided asinput to the VQVAE. The elements of the infrared image set 600 areseparated into colors 602-606. Although three colors are shown in theillustration of FIG. 6 , there may be any number of colors at this stageof processing. Next, the colors 602-606 are converted to temperatures608, 610, 612 and 616. Although four temperatures are shown in theillustration of FIG. 6 , the colors 602-606 may be converted to anynumber of temperatures at this stage of processing. Infrared image setssuch as the IR image set 600 may also be a monochrome as the imagesensor does not distinguish wavelengths of visible light. Therefore,“color” as described herein may be any binary value that can becorrelated to a temperature.

As described above in connection with FIG. 4 , in some examples, theinfrared image processing circuitry 404 leverages emissivity informationto achieve improved thermal anomaly detection accuracy. In FIG. 6 ,pre-stored emissivity information is retrieved from a database.Information from captured images is then matched to the pre-storedemissivity information. For example, a machine learning based objectrecognition technique (e.g., a convolutional neural network) can be usedto recognize an object type (e.g., pipe, flange, cable, etc.), and thenextract emissivity from a database based on object type. In someexamples, a visible image and an infrared camera image can be used todetermine emissivity based on multi-color pyrometry. Inputs can beprovided to the VQVAE 620 for training and/or generation of areconstructed image.

FIG. 7 illustrates example images of the example system to detectthermal anomalies. FIG. 7 includes an example sensor input 702 a, anexample sensor input 704 a, an example reconstructed image 702 b, anexample reconstructed image 704 b, an example ratio image 702 c, anexample ratio image 704 c, an example histogram 702 d, and an examplehistogram 704 d. The sensor input 702 a is an image representative of anunder-cowl environment during normal operating conditions, while thesensor input 704 a is an image of substantially the same area at asecond time, after a thermal anomaly has appeared. Although the sensorinput 702 a and the sensor input 704 a are of the same area, thetechniques described herein also are also effective on images ofdifferent areas and/or areas that have never before been imaged.

The reconstructed image 702 b and the reconstructed image 704 billustrate output of the trained VQVAE 620 of FIG. 6 . The reconstructedimage 702 b is relatively similar to the sensor input 702 a. This isbecause the VQVAE 620 of FIG. 6 was trained (on normal thermal images)to minimize the difference between input and output images. Thus, as thesensor input 702 a is an image of an area without an anomaly, thereconstructed image 702 b has relatively fewer image artifacts. Thereconstructed image 704 b, on the other hand, shows relatively moredistortion and/or artifacts in the image. In this example, this isbecause the area captured in the sensor input 704 a includes a thermalanomaly. As the VQVAE 620 of FIG. 6 was not trained on images withthermal anomalies, the weights and biases of the underlying neuralnetwork do not function to create output with relatively fewerartifacts. The ratio image 702 c illustrates the difference between thesensor input 702 a and the reconstructed image 702 b. The ratio image704 c illustrates the difference between the sensor input 704 a and thereconstructed image 704 b. As there is a greater ratio between thesensor input 704 a and the reconstructed image 704 b, a gaussian curveof the histogram 704 d is relatively wider than that of the histogram702 d.

While an example manner of implementing the analysis server 304 FIG. 3is illustrated in FIG. 4 , one or more of the elements, processes,and/or devices illustrated in FIG. 4 may be combined, divided,re-arranged, omitted, eliminated, and/or implemented in any other way.Further, the example camera controller circuitry 402, the exampleinfrared image processing circuitry 404, the example artificialintelligence circuitry 406, the example network interface circuitry 408,the example image comparator circuitry 410, the example alertingcircuitry 412, the example database managing circuitry 308, and/or theexample analysis server 304 of FIG. 3 , may be implemented by hardware,software, firmware, and/or any combination of hardware, software, and/orfirmware. Thus, for example, any of the example camera controllercircuitry 402, the example infrared image processing circuitry 404, theexample artificial intelligence circuitry 406, the example networkinterface circuitry 408, the example image comparator circuitry 410, theexample alerting circuitry 412, the example database managing circuitry308 and/or, more generally, the example analysis server 304 FIG. 3 ,could be implemented by processor circuitry, analog circuit(s), digitalcircuit(s), logic circuit(s), programmable processor(s), programmablemicrocontroller(s), graphics processing unit(s) (GPU(s)), digital signalprocessor(s) (DSP(s)), application specific integrated circuit(s)(ASIC(s)), programmable logic device(s) (PLD(s)), and/or fieldprogrammable logic device(s) (FPLD(s)) such as Field Programmable GateArrays (FPGAs). When reading any of the apparatus or system claims ofthis patent to cover a purely software and/or firmware implementation,at least one of the example camera controller circuitry 402, the exampleinfrared image processing circuitry 404, the example artificialintelligence circuitry 406, the example network interface circuitry 408,the example image comparator circuitry 410, the example alertingcircuitry 412, the example database managing circuitry 308 is/are herebyexpressly defined to include a non-transitory computer readable storagedevice or storage disk such as a memory, a digital versatile disk (DVD),a compact disk (CD), a Blu-ray disk, etc., including the software and/orfirmware. Further still, the example analysis server 304 of FIG. 3 mayinclude one or more elements, processes, and/or devices in addition to,or instead of, those illustrated in FIG. 4 , and/or may include morethan one of any or all of the illustrated elements, processes anddevices.

A flowchart representative of example hardware logic circuitry, machinereadable instructions, hardware implemented state machines, and/or anycombination thereof for implementing the analysis server 304 of FIG. 3is shown in FIGS. 8-9 . The machine readable instructions may be one ormore executable programs or portion(s) of an executable program forexecution by processor circuitry, such as the processor circuitry 1012shown in the example processor platform 1000 discussed below inconnection with FIG. 10 and/or the example processor circuitry discussedbelow in connection with FIGS. 11 and/or 12 . The program may beembodied in software stored on one or more non-transitory computerreadable storage media such as a CD, a floppy disk, a hard disk drive(HDD), a DVD, a Blu-ray disk, a volatile memory (e.g., Random AccessMemory (RAM) of any type, etc.), or a non-volatile memory (e.g., FLASHmemory, an HDD, etc.) associated with processor circuitry located in oneor more hardware devices, but the entire program and/or parts thereofcould alternatively be executed by one or more hardware devices otherthan the processor circuitry and/or embodied in firmware or dedicatedhardware. The machine readable instructions may be distributed acrossmultiple hardware devices and/or executed by two or more hardwaredevices (e.g., a server and a client hardware device). For example, theclient hardware device may be implemented by an endpoint client hardwaredevice (e.g., a hardware device associated with a user) or anintermediate client hardware device (e.g., a radio access network (RAN)gateway that may facilitate communication between a server and anendpoint client hardware device). Similarly, the non-transitory computerreadable storage media may include one or more mediums located in one ormore hardware devices. Further, although the example program isdescribed with reference to the flowchart illustrated in FIG. 10 , manyother methods of implementing the example analysis server 304 mayalternatively be used. For example, the order of execution of the blocksmay be changed, and/or some of the blocks described may be changed,eliminated, or combined. Additionally or alternatively, any or all ofthe blocks may be implemented by one or more hardware circuits (e.g.,processor circuitry, discrete and/or integrated analog and/or digitalcircuitry, an FPGA, an ASIC, a comparator, an operational-amplifier(opamp), a logic circuit, etc.) structured to perform the correspondingoperation without executing software or firmware. The processorcircuitry may be distributed in different network locations and/or localto one or more hardware devices (e.g., a single-core processor (e.g., asingle core central processor unit (CPU)), a multi-core processor (e.g.,a multi-core CPU), etc.) in a single machine, multiple processorsdistributed across multiple servers of a server rack, multipleprocessors distributed across one or more server racks, a CPU and/or aFPGA located in the same package (e.g., the same integrated circuit (IC)package or in two or more separate housings, etc.).

The machine readable instructions described herein may be stored in oneor more of a compressed format, an encrypted format, a fragmentedformat, a compiled format, an executable format, a packaged format, etc.Machine readable instructions as described herein may be stored as dataor a data structure (e.g., as portions of instructions, code,representations of code, etc.) that may be utilized to create,manufacture, and/or produce machine executable instructions. Forexample, the machine readable instructions may be fragmented and storedon one or more storage devices and/or computing devices (e.g., servers)located at the same or different locations of a network or collection ofnetworks (e.g., in the cloud, in edge devices, etc.). The machinereadable instructions may require one or more of installation,modification, adaptation, updating, combining, supplementing,configuring, decryption, decompression, unpacking, distribution,reassignment, compilation, etc., in order to make them directlyreadable, interpretable, and/or executable by a computing device and/orother machine. For example, the machine readable instructions may bestored in multiple parts, which are individually compressed, encrypted,and/or stored on separate computing devices, wherein the parts whendecrypted, decompressed, and/or combined form a set of machineexecutable instructions that implement one or more operations that maytogether form a program such as that described herein.

In another example, the machine readable instructions may be stored in astate in which they may be read by processor circuitry, but requireaddition of a library (e.g., a dynamic link library (DLL)), a softwaredevelopment kit (SDK), an application programming interface (API), etc.,in order to execute the machine readable instructions on a particularcomputing device or other device. In another example, the machinereadable instructions may need to be configured (e.g., settings stored,data input, network addresses recorded, etc.) before the machinereadable instructions and/or the corresponding program(s) can beexecuted in whole or in part. Thus, machine readable media, as usedherein, may include machine readable instructions and/or program(s)regardless of the particular format or state of the machine readableinstructions and/or program(s) when stored or otherwise at rest or intransit.

The machine readable instructions described herein can be represented byany past, present, or future instruction language, scripting language,programming language, etc. For example, the machine readableinstructions may be represented using any of the following languages: C,C++, Java, C#, Perl, Python, JavaScript, HyperText Markup Language(HTML), Structured Query Language (SQL), Swift, etc.

As mentioned above, the example operations of FIGS. 8-9 may beimplemented using executable instructions (e.g., computer and/or machinereadable instructions) stored on one or more non-transitory computerand/or machine readable media such as optical storage devices, magneticstorage devices, an HDD, a flash memory, a read-only memory (ROM), a CD,a DVD, a cache, a RAM of any type, a register, and/or any other storagedevice or storage disk in which information is stored for any duration(e.g., for extended time periods, permanently, for brief instances, fortemporarily buffering, and/or for caching of the information). As usedherein, the terms non-transitory computer readable medium andnon-transitory computer readable storage medium is expressly defined toinclude any type of computer readable storage device and/or storage diskand to exclude propagating signals and to exclude transmission media.

“Including” and “comprising” (and all forms and tenses thereof) are usedherein to be open ended terms. Thus, whenever a claim employs any formof “include” or “comprise” (e.g., comprises, includes, comprising,including, having, etc.) as a preamble or within a claim recitation ofany kind, it is to be understood that additional elements, terms, etc.,may be present without falling outside the scope of the correspondingclaim or recitation. As used herein, when the phrase “at least” is usedas the transition term in, for example, a preamble of a claim, it isopen-ended in the same manner as the term “comprising” and “including”are open ended. The term “and/or” when used, for example, in a form suchas A, B, and/or C refers to any combination or subset of A, B, C such as(1) A alone, (2) B alone, (3) C alone, (4) A with B, (5) A with C, (6) Bwith C, or (7) A with B and with C. As used herein in the context ofdescribing structures, components, items, objects and/or things, thephrase “at least one of A and B” is intended to refer to implementationsincluding any of (1) at least one A, (2) at least one B, or (3) at leastone A and at least one B. Similarly, as used herein in the context ofdescribing structures, components, items, objects and/or things, thephrase “at least one of A or B” is intended to refer to implementationsincluding any of (1) at least one A, (2) at least one B, or (3) at leastone A and at least one B. As used herein in the context of describingthe performance or execution of processes, instructions, actions,activities and/or steps, the phrase “at least one of A and B” isintended to refer to implementations including any of (1) at least oneA, (2) at least one B, or (3) at least one A and at least one B.Similarly, as used herein in the context of describing the performanceor execution of processes, instructions, actions, activities and/orsteps, the phrase “at least one of A or B” is intended to refer toimplementations including any of (1) at least one A, (2) at least one B,or (3) at least one A and at least one B.

As used herein, singular references (e.g., “a”, “an”, “first”, “second”,etc.) do not exclude a plurality. The term “a” or “an” object, as usedherein, refers to one or more of that object. The terms “a” (or “an”),“one or more”, and “at least one” are used interchangeably herein.Furthermore, although individually listed, a plurality of means,elements or method actions may be implemented by, e.g., the same entityor object. Additionally, although individual features may be included indifferent examples or claims, these may possibly be combined, and theinclusion in different examples or claims does not imply that acombination of features is not feasible and/or advantageous.

FIG. 8 is a flowchart representative of example machine readableinstructions and/or example operations 800 that may be executed and/orinstantiated by processor circuitry to train the artificial intelligencecircuitry 406 (FIG. 4 ). The machine readable instructions and/oroperations 800 of FIG. 8 begin at block 802, when the database managingcircuitry 308 (FIG. 3 ) retrieves normal images from the database 310(FIG. 3 ) to be used in training the artificial intelligence circuitry406 (FIG. 4 ). At block 804, emissivity data from the database is pairedto the thermal images that were retrieved at block 802. The thermalimages are transmitted to the infrared image processing circuitry 404(FIG. 4 ) to be augmented with emissivity data from the database 310(FIG. 3 ). In some examples, objects included in the thermal images aredetected. The detected objects are then matched to objects in thedatabase 310 (FIG. 3 ) with pre-stored emissivity information. Asdescribed in association with FIG. 4 , emissivity data can also beestimated from captured images if there are more than two wavelengthsdetected.

At block 806, input images and emissivity data are provided to theartificial intelligence circuitry 406 (FIG. 4 ). The artificialintelligence circuitry 406 (FIG. 4 ) next operates on the input at block808 to generate a reconstructed image. For example, artificialintelligence circuitry 406 may include a VQVAE with multiple layers ofneurons. As the input data (e.g., input images and emissivity data) istransferred through each layer, a series of operations (e.g.,multiplications and additions) are performed on the data. Additionally,the number of neurons in each layer initially decreases, which generatesa compressed representation of the input data. As the data continuesthrough the VQVAE, the data decompresses as the number of neurons ineach layer increases. The output layer has a similar number of neuronsas the original input, allowing a comparison between the output andinput data.

At block 810, the image comparator circuitry 410 (FIG. 4 ) compares thereconstructed image to the input image, and the artificial intelligencecircuitry 406 (FIG. 4 ) adjusts to lessen the difference between theinput and output image. For example, the difference can be lessened bychanging the weights and biases of layers of the VQVAE based on an error(e.g., difference between input and output images). In some examples,the difference is lessened based on stochastic gradient descent andbackpropagation. At block 812, the artificial intelligence circuitry 406(FIG. 4 ) determines whether additional training images are available.If so, training continues at block 806. Otherwise, control ends at block814.

FIG. 9 is a flowchart representative of example machine readableinstructions and/or example operations 900 that may be executed and/orinstantiated by processor circuitry to operate a vector quantizedvariational autoencoder and/or artificial intelligence circuitry 406.The machine readable instructions and/or operations 900 of FIG. 9 beginat block 902, when the infrared image processing circuitry 404 (FIG. 4 )preprocesses and retrieves a baseline image set from at least oneinfrared camera. In some examples, preprocessing may include imageresizing to ensure all input images are of the same dimensions. In someexamples, preprocessing may include introducing random perturbations tothe images which can reduce plateaus in the training phase.

At block 904, emissivity data is estimated from captured images by theinfrared image processing circuitry 404 (FIG. 4 ). For example, thisestimation can be performed based on multi-color pyrometry. At block906, the input image and emissivity data are provided to the artificialintelligence circuitry 406 (FIG. 4 ). The artificial intelligencecircuitry 406 (FIG. 4 ) next operates on the input at block 908 togenerate a reconstructed image set. As the input data (e.g., inputimages and emissivity data) are transferred through each layer, a seriesof operations (e.g., multiplications and additions) are performed on thedata

At block 910, the image comparator circuitry 410 (FIG. 4 ) calculates aratio between the baseline image set and the reconstructed image set.For example, a ratio could be based on the difference betweencorresponding pixels (e.g., subtracting corresponding pixel values). Atblock 912, the alerting circuitry 412 (FIG. 4 ) determines if the ratiois above a threshold. If the ratio is not above the threshold, theprocess returns to block 902 where a new image set is retrieved.

If, at block 912, the ratio is above a threshold, the alerting circuitry412 (FIG. 4 ) generates an alert at block 914. For example, the alertcan be an entry in a log file for the maintenance or ground crew. Insome examples, the alert can be a visible or audible alert for anaircraft pilot or other user. The example alert could be transmitted bydisplay devices (e.g., to display logged operation information) orinclude activation of a light emitting diode (e.g., to display a warningsignal).

FIG. 10 is a block diagram of an example processor platform 1000structured to execute and/or instantiate the machine readableinstructions and/or operations of FIGS. 8-9 to implement the analysisserver 304 of FIG. 3 . The processor platform 1000 can be, for example,a server, a processor, a custom circuit, or any other type of computingdevice.

The processor platform 1000 of the illustrated example includesprocessor circuitry 1012. The processor circuitry 1012 of theillustrated example is hardware. For example, the processor circuitry1012 can be implemented by one or more integrated circuits, logiccircuits, FPGAs microprocessors, CPUs, GPUs, DSPs, and/ormicrocontrollers from any desired family or manufacturer. The processorcircuitry 1012 may be implemented by one or more semiconductor based(e.g., silicon based) devices. In this example, the processor circuitry1012 implements the example camera controller circuitry 402 (FIG. 4 ),the example infrared image processing circuitry 404 (FIG. 4 ), theexample artificial intelligence circuitry 406 (FIG. 4 ), the examplenetwork interface circuitry 408 (FIG. 4 ), the example image comparatorcircuitry 410 (FIG. 4 ), the example alerting circuitry 412 (FIG. 4 ),and the example database managing circuitry 308 (FIG. 4 ).

The processor circuitry 1012 of the illustrated example includes a localmemory 1013 (e.g., a cache, registers, etc.). The processor circuitry1012 of the illustrated example is in communication with a main memoryincluding a volatile memory 1014 and a non-volatile memory 1016 by a bus1018. The volatile memory 1014 may be implemented by Synchronous DynamicRandom Access Memory (SDRAM), Dynamic Random Access Memory (DRAM),RAMBUS® Dynamic Random Access Memory (RDRAM®), and/or any other type ofRAM device. The non-volatile memory 1016 may be implemented by flashmemory and/or any other desired type of memory device. Access to themain memory 1014, 1016 of the illustrated example is controlled by amemory controller 1017.

The processor platform 1000 of the illustrated example also includesinterface circuitry 1020. The interface circuitry 1020 may beimplemented by hardware in accordance with any type of interfacestandard, such as an Ethernet interface, a universal serial bus (USB)interface, a Bluetooth® interface, a near field communication (NFC)interface, a PCI interface, and/or a PCIe interface.

In the illustrated example, one or more input device(s) 1022 areconnected to the interface circuitry 1020. The input device(s) 1022permit(s) a user to enter data and/or commands into the processorcircuitry 1012. The input device(s) 1022 can be implemented by, forexample, an audio sensor, a microphone, a camera (still or video), akeyboard, a button, a mouse, a touchscreen, a track-pad, and/or a voicerecognition system.

One or more output device(s) 1024 are also connected to the interfacecircuitry 1020 of the illustrated example. The output device(s) 1024 canbe implemented, for example, by display devices (e.g., a light emittingdiode (LED), an organic light emitting diode (OLED), a liquid crystaldisplay (LCD), a cathode ray tube (CRT) display, an in-place switching(IPS) display, a touchscreen, etc.), a tactile output device, a printer,and/or speaker. The interface circuitry 1020 of the illustrated example,thus, typically includes a graphics driver card, a graphics driver chip,and/or graphics processor circuitry such as a GPU.

The interface circuitry 1020 of the illustrated example also includes acommunication device such as a transmitter, a receiver, a transceiver, amodem, a residential gateway, a wireless access point, and/or a networkinterface to facilitate exchange of data with external machines (e.g.,computing devices of any kind) by a network 1026. The communication canbe by, for example, an Ethernet connection, a satellite system, aline-of-site wireless system, a cellular telephone system, an opticalconnection, etc.

The processor platform 1000 of the illustrated example also includes oneor more mass storage devices 1028 to store software and/or data.Examples of such mass storage devices 1028 include magnetic storagedevices, optical storage devices, floppy disk drives, HDDs, CDs, Blu-raydisk drives, redundant array of independent disks (RAID) systems, solidstate storage devices such as flash memory devices, and DVD drives.

Machine executable instructions 1032, which may be implemented by themachine readable instructions of FIGS. 8-9 , may be stored in the massstorage device 1028, in the local memory 1013, in the volatile memory1014, in the non-volatile memory 1016, and/or on a removablenon-transitory computer readable storage medium such as a CD or DVD.

FIG. 11 is a block diagram of an example implementation of the processorcircuitry 1012 of FIG. 10 . In this example, the processor circuitry1012 of FIG. 10 is implemented by a microprocessor 1100. For example,the microprocessor 1100 may implement multi-core hardware circuitry suchas a CPU, a DSP, a GPU, an XPU, etc. Although it may include any numberof example cores 1102 (e.g., 1 core), the microprocessor 1100 of thisexample is a multi-core semiconductor device including N cores. Thecores 1102 of the microprocessor 1100 may operate independently or maycooperate to execute machine readable instructions. For example, machinecode corresponding to a firmware program, an embedded software program,or a software program may be executed by one of the cores 1102 or may beexecuted by multiple ones of the cores 1102 at the same or differenttimes. In some examples, the machine code corresponding to the firmwareprogram, the embedded software program, or the software program is splitinto threads and executed in parallel by two or more of the cores 1102.The software program may correspond to a portion or all of the machinereadable instructions and/or operations represented by the flowchart ofFIGS. 8-9 .

The cores 1102 may communicate by an example bus 1104. In some examples,the bus 1104 may implement a communication bus to effectuatecommunication associated with one(s) of the cores 1102. For example, thebus 1104 may implement at least one of an Inter-Integrated Circuit (I2C)bus, a Serial Peripheral Interface (SPI) bus, a PCI bus, or a PCIe bus.Additionally or alternatively, the bus 1104 may implement any other typeof computing or electrical bus. The cores 1102 may obtain data,instructions, and/or signals from one or more external devices byexample interface circuitry 1106. The cores 1102 may output data,instructions, and/or signals to the one or more external devices by theinterface circuitry 1106. Although the cores 1102 of this exampleinclude example local memory 1120 (e.g., Level 1 (L1) cache that may besplit into an L1 data cache and an L1 instruction cache), themicroprocessor 1100 also includes example shared memory 1110 that may beshared by the cores (e.g., Level 2 (L2_ cache)) for high-speed access todata and/or instructions. Data and/or instructions may be transferred(e.g., shared) by writing to and/or reading from the shared memory 1110.The local memory 1120 of each of the cores 1102 and the shared memory1110 may be part of a hierarchy of storage devices including multiplelevels of cache memory and the main memory (e.g., the main memory 1014,1016 of FIG. 10 ). Typically, higher levels of memory in the hierarchyexhibit lower access time and have smaller storage capacity than lowerlevels of memory. Changes in the various levels of the cache hierarchyare managed (e.g., coordinated) by a cache coherency policy.

Each core 1102 may be referred to as a CPU, DSP, GPU, etc., or any othertype of hardware circuitry. Each core 1102 includes control unitcircuitry 1114, arithmetic and logic (AL) circuitry (sometimes referredto as an Arithmetic Logic Unit ALU) 1116, a plurality of registers 1118,the local memory (L1 cache) 1120, and an example bus 1122. Otherstructures may be present. For example, each core 1102 may includevector unit circuitry, single instruction multiple data (SIMD) unitcircuitry, load/store unit (LSU) circuitry, branch/jump unit circuitry,floating-point unit (FPU) circuitry, etc. The control unit circuitry1114 includes semiconductor-based circuits structured to control (e.g.,coordinate) data movement within the corresponding core 1102. The ALcircuitry 1116 includes semiconductor-based circuits structured toperform one or more mathematic and/or logic operations on the datawithin the corresponding core 1102. The AL circuitry 1116 of someexamples performs integer based operations. In other examples, the ALcircuitry 1116 also performs floating point operations. In yet otherexamples, the AL circuitry 1116 may include first AL circuitry thatperforms integer based operations and second AL circuitry that performsfloating point operations. The registers 1118 are semiconductor-basedstructures to store data and/or instructions such as results of one ormore of the operations performed by the AL circuitry 1116 of thecorresponding core 1102. For example, the registers 1118 may includevector register(s), SIMD register(s), general purpose register(s), flagregister(s), segment register(s), machine specific register(s),instruction pointer register(s), control register(s), debug register(s),memory management register(s), machine check register(s), etc. Theregisters 1118 may be arranged in a bank as shown in FIG. 11 .Alternatively, the registers 1118 may be organized in any otherarrangement, format, or structure including distributed throughout thecore 1102 to shorten access time. The bus 1122 may implement at leastone of an I2C bus, a SPI bus, a PCI bus, or a PCIe bus.

Each core 1102 and/or, more generally, the microprocessor 1100 mayinclude additional and/or alternate structures to those shown anddescribed above. For example, one or more clock circuits, one or morepower supplies, one or more power gates, one or more cache home agents(CHAs), one or more converged/common mesh stops (CMSs), one or moreshifters (e.g., barrel shifter(s)) and/or other circuitry may bepresent. The microprocessor 1100 is a semiconductor device fabricated toinclude many transistors interconnected to implement the structuresdescribed above in one or more integrated circuits (ICs) contained inone or more packages. The processor circuitry may include and/orcooperate with one or more accelerators. In some examples, acceleratorsare implemented by logic circuitry to perform certain tasks more quicklyand/or efficiently than can be done by a general purpose processor.Examples of accelerators include ASICs and FPGAs such as those discussedherein. A GPU or other programmable device can also be an accelerator.Accelerators may be on-board the processor circuitry, in the same chippackage as the processor circuitry and/or in one or more separatepackages from the processor circuitry.

FIG. 12 is a block diagram of another example implementation of theprocessor circuitry 1012 of FIG. 10 . In this example, the processorcircuitry 1012 is implemented by FPGA circuitry 1200. The FPGA circuitry1200 can be used, for example, to perform operations that couldotherwise be performed by the example microprocessor 1100 of FIG. 11executing corresponding machine readable instructions. However, onceconfigured, the FPGA circuitry 1200 instantiates the machine readableinstructions in hardware and, thus, can often execute the operationsfaster than they could be performed by a general purpose microprocessorexecuting the corresponding software.

More specifically, in contrast to the microprocessor 1100 of FIG. 11described above (which is a general purpose device that may beprogrammed to execute some or all of the machine readable instructionsrepresented by the flowcharts of FIGS. 8-9 but whose interconnectionsand logic circuitry are fixed once fabricated), the FPGA circuitry 1200of the example of FIG. 12 includes interconnections and logic circuitrythat may be configured and/or interconnected in different ways afterfabrication to instantiate, for example, some or all of the machinereadable instructions represented by the flowcharts of FIGS. 8-9 . Inparticular, the FPGA 1200 may be thought of as an array of logic gates,interconnections, and switches. The switches can be programmed to changehow the logic gates are interconnected by the interconnections,effectively forming one or more dedicated logic circuits (unless anduntil the FPGA circuitry 1200 is reprogrammed). The configured logiccircuits enable the logic gates to cooperate in different ways toperform different operations on data received by input circuitry. Thoseoperations may correspond to some or all of the software represented bythe flowcharts of FIGS. 8-9 . As such, the FPGA circuitry 1200 may bestructured to effectively instantiate some or all of the machinereadable instructions of the flowcharts of FIGS. 8-9 as dedicated logiccircuits to perform the operations corresponding to those softwareinstructions in a dedicated manner analogous to an ASIC. Therefore, theFPGA circuitry 1200 may perform the operations corresponding to the someor all of the machine readable instructions of FIGS. 8-9 faster than thegeneral purpose microprocessor can execute the same.

In the example of FIG. 12 , the FPGA circuitry 1200 is structured to beprogrammed (and/or reprogrammed one or more times) by an end user by ahardware description language (HDL) such as Verilog. The FPGA circuitry1200 of FIG. 12 , includes example input/output (I/O) circuitry 1202 toobtain and/or output data to/from example configuration circuitry 1204and/or external hardware (e.g., external hardware circuitry) 1206. Forexample, the configuration circuitry 1204 may implement interfacecircuitry that may obtain machine readable instructions to configure theFPGA circuitry 1200, or portion(s) thereof. In some such examples, theconfiguration circuitry 1204 may obtain the machine readableinstructions from a user, a machine (e.g., hardware circuitry (e.g.,programmed or dedicated circuitry) that may implement an ArtificialIntelligence/Machine Learning (AI/ML) model to generate theinstructions), etc. In some examples, the external hardware 1206 mayimplement the microprocessor 1100 of FIG. 11 . The FPGA circuitry 1200also includes an array of example logic gate circuitry 1208, a pluralityof example configurable interconnections 1210, and example storagecircuitry 1212. The logic gate circuitry 1208 and interconnections 1210are configurable to instantiate one or more operations that maycorrespond to at least some of the machine readable instructions ofFIGS. 8-9 and/or other desired operations. The logic gate circuitry 1208shown in FIG. 12 is fabricated in groups or blocks. Each block includessemiconductor-based electrical structures that may be configured intologic circuits. In some examples, the electrical structures includelogic gates (e.g., And gates, Or gates, Nor gates, etc.) that providebasic building blocks for logic circuits. Electrically controllableswitches (e.g., transistors) are present within each of the logic gatecircuitry 1208 to enable configuration of the electrical structuresand/or the logic gates to form circuits to perform desired operations.The logic gate circuitry 1208 may include other electrical structuressuch as look-up tables (LUTs), registers (e.g., flip-flops or latches),multiplexers, etc.

The interconnections 1210 of the illustrated example are conductivepathways, traces, vias, or the like that may include electricallycontrollable switches (e.g., transistors) whose state can be changed byprogramming (e.g., using an HDL instruction language) to activate ordeactivate one or more connections between one or more of the logic gatecircuitry 1208 to program desired logic circuits.

The storage circuitry 1212 of the illustrated example is structured tostore result(s) of the one or more of the operations performed bycorresponding logic gates. The storage circuitry 1212 may be implementedby registers or the like. In the illustrated example, the storagecircuitry 1212 is distributed amongst the logic gate circuitry 1208 tofacilitate access and increase execution speed.

The example FPGA circuitry 1200 of FIG. 12 also includes exampleDedicated Operations Circuitry 1214. In this example, the DedicatedOperations Circuitry 1214 includes special purpose circuitry 1216 thatmay be invoked to implement commonly used functions to avoid the need toprogram those functions in the field. Examples of such special purposecircuitry 1216 include memory (e.g., DRAM) controller circuitry, PCIecontroller circuitry, clock circuitry, transceiver circuitry, memory,and multiplier-accumulator circuitry. Other types of special purposecircuitry may be present. In some examples, the FPGA circuitry 1200 mayalso include example general purpose programmable circuitry 1218 such asan example CPU 1220 and/or an example DSP 1222. Other general purposeprogrammable circuitry 1218 may additionally or alternatively be presentsuch as a GPU, an XPU, etc., that can be programmed to perform otheroperations.

Although FIGS. 11 and 12 illustrate two example implementations of theprocessor circuitry 1012 of FIG. 10 , many other approaches arecontemplated. For example, as mentioned above, modern FPGA circuitry mayinclude an on-board CPU, such as one or more of the example CPU 1220 ofFIG. 12 . Therefore, the processor circuitry 1000 of FIG. 10 mayadditionally be implemented by combining the example microprocessor 1100of FIG. 11 and the example FPGA circuitry 1200 of FIG. 12 . In some suchhybrid examples, a first portion of the machine readable instructionsrepresented by the flowchart of FIGS. 8-9 may be executed by one or moreof the cores 1102 of FIG. 11 and a second portion of the machinereadable instructions represented by the flowcharts of FIGS. 8-9 may beexecuted by the FPGA circuitry 1200 of FIG. 12 .

In some examples, the processor circuitry 1012 of FIG. 10 may be in oneor more packages. For example, the microprocessor 1100 of FIG. 11 and/orthe FPGA circuitry 1200 of FIG. 12 may be in one or more packages. Insome examples, an XPU may be implemented by the processor circuitry 1012of FIG. 10 , which may be in one or more packages. For example, the XPUmay include a CPU in one package, a DSP in another package, a GPU in yetanother package, and an FPGA in still yet another package.

From the foregoing, it will be appreciated that example systems,methods, apparatus, and articles of manufacture have been disclosed thatfacilitate autonomous detection of leaks across distributed infraredcamera sources. The disclosed systems, methods, apparatus, and articlesof manufacture improve the efficiency of detecting thermal anomalies inthe under-cowl area of a gas turbine engine. In some examples,generating two-dimensional heat maps allows substantially real timeanomaly detection by distributed sensors. Examples disclosed hereincoordinate sensors more effectively, decreasing thermal anomaly testingtime and increasing anomaly detection accuracy. Additionally, byproviding both emissivity and image data to a variational autoencoder,the detection rate of thermal anomalies can be improved.

Although certain example systems, methods, apparatus, and articles ofmanufacture have been disclosed herein, the scope of coverage of thispatent is not limited thereto. On the contrary, this patent covers allsystems, methods, apparatus, and articles of manufacture fairly fallingwithin the scope of the claims of this patent.

Further aspects of the present disclosure are provided by the subjectmatter of the following clauses:

An apparatus to detect engine anomalies comprising at least one memoryto store instructions, and processor circuitry to execute theinstructions to control a plurality of infrared cameras to capture abaseline image set, the baseline image set including at least twothermal images, generate emissivity data based on the baseline imageset, provide the baseline image set and the emissivity data to anartificial intelligence model, the artificial intelligence model togenerate a reconstructed image set, determine a difference between thebaseline image set and the reconstructed image set, and in response tothe difference exceeding a threshold, generate an alert indicatingdetection of an engine anomaly.

The apparatus of any preceding clause, wherein the artificialintelligence model includes at least one of a variational autoencoderand a generative adversarial neural network.

The apparatus of any preceding clause, wherein the difference isdetermined based on a ratio of a first image of the baseline image setto a second image of the reconstructed image set.

The apparatus of any preceding clause, wherein in response to a firstcamera of the plurality of infrared cameras detecting an anomaly, theprocessor circuitry is to execute the instructions to direct a secondcamera of the plurality of infrared cameras to image the anomaly.

The apparatus of any preceding clause, wherein to generate theemissivity data incudes at least one of associating a recognized objectwith an emissivity value stored in a database, and applying multi-colorpyrometry to electromagnetic radiation of two different wavelengthbands.

The apparatus of any preceding clause, wherein the processor circuitryis to execute the instructions to generate a two-dimensional temperaturemap.

The apparatus of any preceding clause, wherein the engine is a gasturbine engine and the anomaly is an engine leak in the under cowl areaof the gas turbine engine.

A non-transitory computer readable medium comprising instructions,which, when executed, cause processor circuitry to at least control aplurality of infrared cameras to capture a baseline image set, thebaseline image set including at least two thermal images, generateemissivity data based on the baseline image set, provide the baselineimage set and the emissivity data to an artificial intelligence model,the artificial intelligence model to generate a reconstructed image set,determine a difference between the baseline image set and thereconstructed image set, and in response to the difference exceeding athreshold, generate an alert indicating detection of an engine anomalyexample 9 includes the non-transitory computer readable medium ofexample 8, wherein the unsupervised artificial intelligence modelincludes at least one of a variational autoencoder and a generativeadversarial neural network.

The non-transitory computer readable medium of any preceding clause,wherein the difference is determined based on a ratio of a first imageof the baseline image set to a second image of the reconstructed imageset.

The non-transitory computer readable medium of any preceding clause,wherein in response to a first camera of the plurality of infraredcameras detecting an anomaly, the processor circuitry is to execute theinstructions to direct a second camera of the plurality of infraredcameras to image the anomaly.

The non-transitory computer readable medium of any preceding clause,wherein to generate the emissivity data incudes at least one ofassociating a recognized object with an emissivity value stored in adatabase, and applying multi-color pyrometry to electromagneticradiation of two different wavelength bands.

The non-transitory computer readable medium of any preceding clause,wherein the processor circuitry is to execute the instructions togenerate a two-dimensional temperature map.

The non-transitory computer readable medium of any preceding clause,wherein the engine is a gas turbine engine and the anomaly is an engineleak in the under cowl area of the gas turbine engine.

A method comprising controlling a plurality of infrared cameras tocapture a baseline image set, the baseline image set including at leasttwo thermal images, generating emissivity data based on the baselineimage set, providing the baseline image set and the emissivity data toan artificial intelligence model, the artificial intelligence model togenerate a reconstructed image set, determining a difference between thebaseline image set and the reconstructed image set, and in response tothe difference exceeding a threshold, generating an alert indicatingdetection of an engine anomaly example 16 includes the method of example15, wherein the artificial intelligence model includes at least one of avariational autoencoder and a generative adversarial neural network.

The method of any preceding clause, wherein determining the differenceis based on a ratio of a first image of the baseline image set to asecond image of the reconstructed image set.

The method of any preceding clause, wherein generating the emissivitydata incudes at least one of associating a recognized object with anemissivity value stored in a database, and applying multi-colorpyrometry to electromagnetic radiation of two different wavelengthbands.

The method of any preceding clause, wherein the processor circuitry isto execute the instructions to generate a two-dimensional temperaturemap.

The method of any preceding clause, wherein the engine is a gas turbineengine and the anomaly is an engine leak in the under cowl area of thegas turbine engine.

The following claims are hereby incorporated into this DetailedDescription by this reference, with each claim standing on its own as aseparate embodiment of the present disclosure.

What is claimed is:
 1. An apparatus to detect engine anomaliescomprising: at least one memory to store instructions; and processorcircuitry to execute the instructions to: control a plurality ofinfrared cameras to capture a baseline image set, the baseline image setincluding at least two thermal images; generate emissivity data based onthe baseline image set; provide the baseline image set and theemissivity data to an artificial intelligence model, the artificialintelligence model to generate a reconstructed image set; determine adifference between the baseline image set and the reconstructed imageset; and in response to the difference exceeding a threshold, generatean alert indicating detection of an engine anomaly.
 2. The apparatus ofclaim 1, wherein the artificial intelligence model includes at least oneof a variational autoencoder and a generative adversarial neuralnetwork.
 3. The apparatus of claim 1, wherein the difference isdetermined based on a ratio of an image of the baseline image set to animage of the reconstructed image set.
 4. The apparatus of claim 1,wherein in response to a first camera of the plurality of infraredcameras detecting the engine anomaly, the processor circuitry is toexecute the instructions to direct a second camera of the plurality ofinfrared cameras to image the engine anomaly.
 5. The apparatus of claim1, wherein to generate the emissivity data incudes at least one of:associating a recognized object with an emissivity value stored in adatabase; and applying multi-color pyrometry to electromagneticradiation of two different wavelength bands.
 6. The apparatus of claim1, wherein the processor circuitry is to execute the instructions togenerate a two-dimensional temperature map.
 7. The apparatus of claim 1,wherein the engine anomaly is an engine leak in an under cowl area of agas turbine engine.
 8. A non-transitory computer readable mediumcomprising instructions, which, when executed, cause processor circuitryto at least: control a plurality of infrared cameras to capture abaseline image set, the baseline image set including at least twothermal images; generate emissivity data based on the baseline imageset; provide the baseline image set and the emissivity data to anartificial intelligence model, the artificial intelligence model togenerate a reconstructed image set; determine a difference between thebaseline image set and the reconstructed image set; and in response tothe difference exceeding a threshold, generate an alert indicatingdetection of an engine anomaly.
 9. The non-transitory computer readablemedium of claim 8, wherein the unsupervised artificial intelligencemodel includes at least one of a variational autoencoder and agenerative adversarial neural network.
 10. The non-transitory computerreadable medium of claim 8, wherein the difference is determined basedon a ratio of an image of the baseline image set to an image of thereconstructed image set.
 11. The non-transitory computer readable mediumof claim 8, wherein in response to a first camera of the plurality ofinfrared cameras detecting the engine anomaly, the processor circuitryis to execute the instructions to direct a second camera of theplurality of infrared cameras to image the engine anomaly.
 12. Thenon-transitory computer readable medium of claim 8, wherein to generatethe emissivity data incudes at least one of: associating a recognizedobject with an emissivity value stored in a database; and applyingmulti-color pyrometry to electromagnetic radiation of two differentwavelength bands.
 13. The non-transitory computer readable medium ofclaim 8, wherein the processor circuitry is to execute the instructionsto generate a two-dimensional temperature map.
 14. The non-transitorycomputer readable medium of claim 8, wherein the engine anomaly is anengine leak in an under cowl area of a gas turbine engine.
 15. A methodcomprising: controlling a plurality of infrared cameras to capture abaseline image set, the baseline image set including at least twothermal images; generating emissivity data based on the baseline imageset; providing the baseline image set and the emissivity data to anartificial intelligence model, the artificial intelligence model togenerate a reconstructed image set; determining a difference between thebaseline image set and the reconstructed image set; and in response tothe difference exceeding a threshold, generating an alert indicatingdetection of an engine anomaly.
 16. The method of claim 15, wherein theartificial intelligence model includes at least one of a variationalautoencoder and a generative adversarial neural network.
 17. The methodof claim 15, wherein determining the difference is based on a ratio ofan image of the baseline image set to an image of the reconstructedimage set.
 18. The method of claim 15, wherein generating the emissivitydata incudes at least one of: associating a recognized object with anemissivity value stored in a database; and applying multi-colorpyrometry to electromagnetic radiation of two different wavelengthbands.
 19. The method of claim 15, wherein the processor circuitry is toexecute the instructions to generate a two-dimensional temperature map.20. The method of claim 15, wherein the engine anomaly is an engine leakin an under cowl area of a gas turbine engine.